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Some good explanation on serial port FIFO issues I just came across -
Note that this is an old posting - todays computer can cycle the IRQ
more often.
"Albert P. Belle Isle" <belleisl@xxxxxxxxxxxxxxxx>
wrote about {Re: high speed modems ?????} in
'comp.dcom.modems'...
~> Most PC's can service between 1,000 and 1,200
IRQ's per second. Multiply ~>this by the size of a
16550 buffer (16) and all you get is 19,200 cps.
Isn't ~>this is a little short of the 23,040 cps
advertised for the 28.8's? ~>
~Ed:
~If you set RxTrigger for the FIFO to only 1 byte,
then there will only be ~1 byte for the CPU to empty
from the UART when it goes to answer the IRQ.
~However, if you set the RxTrigger to a higher
value, like the Windows ~comm.drv default of 8, then
the UART will wait until the FIFO has that ~many
bytes in it before raising the IRQ. That number of
bytes will then ~be taken off in a burst when the
IRQ is serviced.
~That's the design idea behind adding the FIFO
buffer to the UART: to get ~around the very problem
you mentioned.
==============================================
I understand and totally agree. However, if you only
have a total of 1,200 IRQ's per second available
(BIOS limit) and you multiply this by the full
16-byte UART buffer size you come up with a 'maximum
theoretical DTE rate' of 19,200 bytes/sec. This is
about 3,840 bytes/sec short of the advertised 23,040
rate for a 28.8-LAPM compliant modem. My RxFIFO is
set at 14.
Ed..
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** Common Sense Is Not Common **
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